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4-11 mt8870d/MT8870D-1 integrated dtmf receiver features ? complete dtmf receiver ? low power consumption ? internal gain setting ampli?er ? adjustable guard time ? central of?ce quality ? power-down mode ? inhibit mode ? backward compatible with mt8870c/mt8870c-1 applications ? receiver system for british telecom (bt) or cept spec (MT8870D-1) ? paging systems ? repeater systems/mobile radio ? credit card systems ? remote control ? personal computers ? telephone answering machine description the mt8870d/MT8870D-1 is a complete dtmf receiver integrating both the bandsplit ?lter and digital decoder functions. the ?lter section uses switched capacitor techniques for high and low group ?lters; the decoder uses digital counting techniques to detect and decode all 16 dtmf tone- pairs into a 4-bit code. external component count is minimized by on chip provision of a differential input ampli?er, clock oscillator and latched three-state bus interface. ordering information mt8870de/de-1 18 pin plastic dip mt8870ds/ds-1 18 pin soic mt8870dn/dn-1 20 pin ssop -40 c to +85 c figure 1 - functional block diagram pwdn in + in - gs osc1 osc2 st/gt est std toe q1 q2 q3 q4 vdd vss vref inh bias circuit dial tone filter high group filter low group filter digital detection algorithm code converter and latch st gt steering logic chip power chip bias vref buffer zero crossing detectors to all chip clocks issue 5 march 1997 iso 2 -cmos
mt8870d/MT8870D-1 iso 2 -cmos 4-12 figure 2 - pin connections pin description pin # name description 18 20 1 1 in+ non-inverting op-amp (input) . 2 2 in- inverting op-amp (input) . 33 gs gain select. gives access to output of front end differential ampli?er for connection of feedback resistor. 44 v ref reference voltage (output). nominally v dd /2 is used to bias inputs at mid-rail (see fig. 6 and fig. 10). 5 5 inh inhibit (input). logic high inhibits the detection of tones representing characters a, b, c and d. this pin input is internally pulled down. 6 6 pwdn power down (input). active high. powers down the device and inhibits the oscillator. this pin input is internally pulled down. 7 8 osc1 clock (input) . 8 9 osc2 clock (output) . a 3.579545 mhz crystal connected between pins osc1 and osc2 completes the internal oscillator circuit. 910 v ss ground (input) . 0v typical. 10 11 toe three state output enable (input). logic high enables the outputs q1-q4. this pin is pulled up internally. 11- 14 12- 15 q1-q4 three state data (output). when enabled by toe, provide the code corresponding to the last valid tone-pair received (see table 1). when toe is logic low, the data outputs are high impedance. 15 17 std delayed steering (output). presents a logic high when a received tone-pair has been registered and the output latch updated; returns to logic low when the voltage on st/gt falls below v tst . 16 18 est early steering (output). presents a logic high once the digital algorithm has detected a valid tone pair (signal condition). any momentary loss of signal condition will cause est to return to a logic low. 17 19 st/gt steering input/guard time (output) bidirectional. a voltage greater than v tst detected at st causes the device to register the detected tone pair and update the output latch. a voltage less than v tst frees the device to accept a new tone pair. the gt output acts to reset the external steering time-constant; its state is a function of est and the voltage on st. 18 20 v dd positive power supply (input) . +5v typical. 7, 16 nc no connection. 1 2 3 4 5 6 7 8 9 10 18 17 16 15 14 13 12 11 in+ in- gs vref inh pwdn osc1 osc2 vss vdd st/gt est std q4 q3 q2 q1 toe 18 pin plastic dip/soic 1 2 3 4 5 6 7 8 9 10 11 12 20 19 18 17 16 15 14 13 in+ in- gs vref inh pwdn nc osc1 osc2 vss 20 pin ssop vdd st/gt est std q4 q3 q2 q1 toe nc
iso 2 -cmos mt8870d/MT8870D-1 4-13 functional description the mt8870d/MT8870D-1 monolithic dtmf receiver offers small size, low power consumption and high performance. its architecture consists of a bandsplit ?lter section, which separates the high and low group tones, followed by a digital counting section which veri?es the frequency and duration of the received tones before passing the corresponding code to the output bus. filter section separation of the low-group and high group tones is achieved by applying the dtmf signal to the inputs of two sixth-order switched capacitor bandpass ?lters, the bandwidths of which correspond to the low and high group frequencies. the ?lter section also incorporates notches at 350 and 440 hz for exceptional dial tone rejection (see figure 3). each ?lter output is followed by a single order switched capacitor ?lter section which smooths the signals prior to limiting. limiting is performed by high-gain comparators which are provided with hysteresis to prevent detection of unwanted low-level signals. the outputs of the comparators provide full rail logic swings at the frequencies of the incoming dtmf signals. decoder section following the ?lter section is a decoder employing digital counting techniques to determine the frequencies of the incoming tones and to verify that they correspond to standard dtmf frequencies. a complex averaging algorithm protects against tone simulation by extraneous signals such as voice while figure 4 - basic steering circuit providing tolerance to small frequency deviations and variations. this averaging algorithm has been developed to ensure an optimum combination of immunity to talk-off and tolerance to the presence of interfering frequencies (third tones) and noise. when the detector recognizes the presence of two valid tones (this is referred to as the signal condition in some industry speci?cations) the early steering (est) output will go to an active state. any subsequent loss of signal condition will cause est to assume an inactive state (see steering circuit). steering circuit before registration of a decoded tone pair, the receiver checks for a valid signal duration (referred to as character recognition condition). this check is performed by an external rc time constant driven by est. a logic high on est causes v c (see figure 4) to rise as the capacitor discharges. provided signal v dd c v c v dd st/gt est std mt8870d/ MT8870D-1 r t gta =(rc)in(v dd /v tst ) t gtp =(rc)in[v dd /(v dd -v tst )] figure 3 - filter response 0 10 20 30 40 50 attenuation (db) xy abcd 1khz ef g h precise dial tones x=350 hz y=440 hz dtmf tones a=697 hz b=770 hz c=852 hz d=941 hz e=1209 hz f=1336 hz g=1477 hz h=1633 hz frequency (hz)
mt8870d/MT8870D-1 iso 2 -cmos 4-14 condition is maintained (est remains high) for the validation period (t gtp ), v c reaches the threshold (v tst ) of the steering logic to register the tone pair, latching its corresponding 4-bit code (see table 1) into the output latch. at this point the gt output is activated and drives v c to v dd . gt continues to drive high as long as est remains high. finally, after a short delay to allow the output latch to settle, the delayed steering output ?ag (std) goes high, signalling that a received tone pair has been registered. the contents of the output latch are made available on the 4-bit output bus by raising the three state control input (toe) to a logic high. the steering circuit works in reverse to validate the interdigit pause between signals. thus, as well as rejecting signals too short to be considered valid, the receiver will tolerate signal interruptions (dropout) too short to be considered a valid pause. this facility, together with the capability of selecting the steering time constants externally, allows the designer to tailor performance to meet a wide variety of system requirements. guard time adjustment in many situations not requiring selection of tone duration and interdigital pause, the simple steering circuit shown in figure 4 is applicable. component values are chosen according to the formula: t rec =t dp +t gtp t id =t da +t gta the value of t dp is a device parameter (see figure 11) and t rec is the minimum signal duration to be recognized by the receiver. a value for c of 0.1 m f is figure 5 - guard time adjustment table 1. functional decode table l=logic low, h=logic high, z=high impedance x = dont care recommended for most applications, leaving r to be selected by the designer. different steering arrangements may be used to select independently the guard times for tone present (t gtp ) and tone absent (t gta ). this may be necessary to meet system speci?cations which place both accept and reject limits on both tone duration and interdigital pause. guard time adjustment also allows the designer to tailor system parameters such as talk off and noise immunity. increasing t rec improves talk-off performance since it reduces the probability that tones simulated by speech will maintain signal condition long enough to be registered. alternatively, a relatively short t rec with a long t do would be appropriate for extremely noisy environments where fast acquisition time and immunity to tone drop-outs are required. design information for guard time adjustment is shown in figure 5. v dd st/gt est c 1 r 1 r 2 a) decreasing t gtp ; (t gtp t gta ) digit toe inh est q 4 q 3 q 2 q 1 anylxhzzzz 1hxh0001 2hxh0010 3hxh0011 4hxh0100 5hxh0101 6hxh0110 7hxh0111 8hxh1000 9hxh1001 0hxh1010 *hxh1011 #hxh1100 ahlh1101 bhlh1110 chlh1111 dhlh0000 ahhl undetected, the output code will remain the same as the previous detected code bhhl chhl dhhl
iso 2 -cmos mt8870d/MT8870D-1 4-15 power-down and inhibit mode a logic high applied to pin 6 (pwdn) will power down the device to minimize the power consumption in a standby mode. it stops the oscillator and the functions of the ?lters. inhibit mode is enabled by a logic high input to the pin 5 (inh). it inhibits the detection of tones representing characters a, b, c, and d. the output code will remain the same as the previous detected code (see table 1). differential input con?guration the input arrangement of the mt8870d/MT8870D-1 provides a differential-input operational ampli?er as well as a bias source (v ref ) which is used to bias the inputs at mid-rail. provision is made for connection of a feedback resistor to the op-amp output (gs) for adjustment of gain. in a single-ended con?guration, the input pins are connected as shown in figure 10 with the op-amp connected for unity gain and v ref biasing the input at 1 / 2 v dd . figure 6 shows the differential con?guration, which permits the adjustment of gain with the feedback resistor r 5 . crystal oscillator the internal clock circuit is completed with the addition of an external 3.579545 mhz crystal and is normally connected as shown in figure 10 (single- ended input con?guration). however, it is possible to con?gure several mt8870d/MT8870D-1 devices employing only a single oscillator crystal. the oscillator output of the ?rst device in the chain is coupled through a 30 pf capacitor to the oscillator input (osc1) of the next device. subsequent devices are connected in a similar fashion. refer to figure 7 for details. the problems associated with unbalanced loading are not a concern with the arrangement shown, i.e., precision balancing capacitors are not required. figure 6 - differential input con?guration figure 7 - oscillator connection table 2. recommended resonator speci?cations note: qm=quality factor of rlc model, i.e., 1/2 p| r1c1. parameter unit resonator r1 ohms 10.752 l1 mh .432 c1 pf 4.984 c0 pf 37.915 qm - 896.37 d f% 0.2% c 1 r 1 c 2 r 4 r 3 in+ in- + - r 5 gs r 2 v ref mt8870d/ MT8870D-1 differential input amplifier c 1 =c 2 =10 nf r 1 =r 4 =r 5 =100 k w r 2 =60k w , r 3 =37.5 k w all resistors are 1% tolerance. all capacitors are 5% tolerance. r 3 = r 2 r 5 r 2 +r 5 voltage gain (a v diff)= r 5 r 1 input impedance (z indiff ) = 2 r 1 2 + 1 w c 2 osc1 osc2 osc2 osc1 c x-tal c to osc1 of next mt8870d/MT8870D-1 c=30 pf x-tal=3.579545 mhz
mt8870d/MT8870D-1 iso 2 -cmos 4-16 applications receiver system for british telecom spec por 1151 the circuit shown in fig. 9 illustrates the use of MT8870D-1 device in a typical receiver system. bt spec de?nes the input signals less than -34 dbm as the non-operate level. this condition can be attained by choosing a suitable values of r 1 and r 2 to provide 3 db attenuation, such that -34 dbm input signal will correspond to -37 dbm at the gain setting pin gs of MT8870D-1. as shown in the diagram, the component values of r 3 and c 2 are the guard time requirements when the total component tolerance is 6%. for better performance, it is recommended to use the non-symmetric guard time circuit in fig. 8. figure 8 - non-symmetric guard time circuit t gtp =(r p c 1 )in[v dd /(v dd -v tst )] t gta =(r 1 c 1 )in(v dd /v tst ) r p =(r 1 r 2 )/(r 1 +r 2 ) v dd st/gt est c 1 r 2 r 1 notes: r 1 =368k w 1% r 2 =2.2m w 1% c 1 =100nf 5% figure 9 - single-ended input con?guration for bt or cept spec in+ in- gs v ref inh pwdn osc 1 osc 2 v ss toe v dd st/gt est std q4 q3 q2 q1 dtmf input c 1 r 1 r 2 x 1 v dd c 2 r 3 MT8870D-1 notes: r 1 = 102k w 1% r 2 = 71.5k w 1% r 3 = 390k w 1 % c 1 ,c 2 = 100 nf 5% x 1 = 3.579545 mhz 0.1% v dd = 5.0v 5%
iso 2 -cmos mt8870d/MT8870D-1 4-17 ? exceeding these values may cause permanent damage. functional operation under these conditions is not implied. derate above 75 c at 16 mw / c. all leads soldered to board. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. absolute maximum ratings ? parameter symbol min max units 1 dc power supply voltage v dd 7v 2 voltage on any pin v i v ss -0.3 v dd +0.3 v 3 current at any pin (other than supply) i i 10 ma 4 storage temperature t stg -65 +150 c 5 package power dissipation p d 500 mw recommended operating conditions - voltages are with respect to ground (v ss ) unless otherwise stated. parameter sym min typ ? max units test conditions 1 dc power supply voltage v dd 4.75 5.0 5.25 v 2 operating temperature t o -40 +85 c 3 crystal/clock frequency fc 3.579545 mhz 4 crystal/clock freq.tolerance d fc 0.1 % dc electrical characteristics - v dd =5.0v 5%, v ss =0v, -40 c t o +85 c, unless otherwise stated. characteristics sym min typ ? max units test conditions 1 s u p p l y standby supply current i ddq 10 25 m a pwdn=v dd 2 operating supply current i dd 3.0 9.0 ma 3 power consumption p o 15 mw fc=3.579545 mhz 4 i n p u t s high level input v ih 3.5 v v dd =5.0v 5 low level input voltage v il 1.5 v v dd =5.0v 6 input leakage current i ih /i il 0.1 m av in =v ss or v dd 7 pull up (source) current i so 7.5 20 m a toe (pin 10)=0, v dd =5.0v 8 pull down (sink) current i si 15 45 m a inh=5.0v, pwdn=5.0v, v dd =5.0v 9 input impedance (in+, in-) r in 10 m w @ 1 khz 10 steering threshold voltage v tst 2.2 2.4 2.5 v v dd = 5.0v 11 o u t p u t s low level output voltage v ol v ss +0.03 v no load 12 high level output voltage v oh v dd -0.03 v no load 13 output low (sink) current i ol 1.0 2.5 ma v out =0.4 v 14 output high (source) current i oh 0.4 0.8 ma v out =4.6 v 15 v ref output voltage v ref 2.3 2.5 2.7 v no load, v dd = 5.0v 16 v ref output resistance r or 1k w
mt8870d/MT8870D-1 iso 2 -cmos 4-18 ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. * notes 1. dbm= decibels above or below a reference power of 1 mw into a 600 ohm load. 2. digit sequence consists of all dtmf tones. 3. tone duration= 40 ms, tone pause= 40 ms. 4. signal condition consists of nominal dtmf frequencies. 5. both tones in composite signal have an equal amplitude. 6. tone pair is deviated by 1.5 % 2 hz. 7. bandwidth limited (3 khz ) gaussian noise. 8. the precise dial tone frequencies are (350 hz and 440 hz) 2 %. 9. for an error rate of better than 1 in 10,000. 10. referenced to lowest level frequency component in dtmf signal. 11. referenced to the minimum valid accept level. 12. guaranteed by design and characterization. operating characteristics - v dd =5.0v 5%, v ss =0v, -40 c t o +85 c ,unless otherwise stated. gain setting ampli?er characteristics sym min typ ? max units test conditions 1 input leakage current i in 100 na v ss v in v dd 2 input resistance r in 10 m w 3 input offset voltage v os 25 mv 4 power supply rejection psrr 50 db 1 khz 5 common mode rejection cmrr 40 db 0.75 v v in 4.25 v biased at v ref =2.5 v 6 dc open loop voltage gain a vol 32 db 7 unity gain bandwidth f c 0.30 mhz 8 output voltage swing v o 4.0 v pp load 3 100 k w to v ss @ gs 9 maximum capacitive load (gs) c l 100 pf 10 resistive load (gs) r l 50 k w 11 common mode range v cm 2.5 v pp no load mt8870d ac electrical characteristics -v dd =5.0v 5%, v ss =0v, -40 c t o +85 c , using test circuit shown in figure 10. characteristics sym min typ ? max units notes* 1 valid input signal levels (each tone of composite signal) -29 +1 dbm 1,2,3,5,6,9 27.5 869 mv rms 1,2,3,5,6,9 2 negative twist accept 8 db 2,3,6,9,12 3 positive twist accept 8 db 2,3,6,9,12 4 frequency deviation accept 1.5% 2 hz 2,3,5,9 5 frequency deviation reject 3.5% 2,3,5,9 6 third tone tolerance -16 db 2,3,4,5,9,10 7 noise tolerance -12 db 2,3,4,5,7,9,10 8 dial tone tolerance +22 db 2,3,4,5,8,9,11
iso 2 -cmos mt8870d/MT8870D-1 4-19 ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. * notes 1. dbm= decibels above or below a reference power of 1 mw into a 600 ohm load. 2. digit sequence consists of all dtmf tones. 3. tone duration= 40 ms, tone pause= 40 ms. 4. signal condition consists of nominal dtmf frequencies. 5. both tones in composite signal have an equal amplitude. 6. tone pair is deviated by 1.5 % 2 hz. 7. bandwidth limited (3 khz ) gaussian noise. 8. the precise dial tone frequencies are (350 hz and 440 hz) 2 %. 9. for an error rate of better than 1 in 10,000. 10. referenced to lowest level frequency component in dtmf signal. 11. referenced to the minimum valid accept level. 12. referenced to fig. 10 input dtmf tone level at -25dbm (-28dbm at gs pin) interference frequency range between 480-3400hz. 13. guaranteed by design and characterization. MT8870D-1 ac electrical characteristics -v dd =5.0v 5%, v ss =0v, -40 c t o +85 c , using test circuit shown in figure 10. characteristics sym min typ ? max units notes* 1 valid input signal levels (each tone of composite signal) -31 +1 dbm tested at v dd =5.0v 1,2,3,5,6,9 21.8 869 mv rms 2 input signal level reject -37 dbm tested at v dd =5.0v 1,2,3,5,6,9 10.9 mv rms 3 negative twist accept 8 db 2,3,6,9,13 4 positive twist accept 8 db 2,3,6,9,13 5 frequency deviation accept 1.5% 2 hz 2,3,5,9 6 frequency deviation reject 3.5% 2,3,5,9 7 third zone tolerance -18.5 db 2,3,4,5,9,12 8 noise tolerance -12 db 2,3,4,5,7,9,10 9 dial tone tolerance +22 db 2,3,4,5,8,9,11
mt8870d/MT8870D-1 iso 2 -cmos 4-20 ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. *notes: 1. used for guard-time calculation purposes only. 2. these, user adjustable parameters, are not device speci?cations. the adjustable settings of these minimums and maximums are recommendations based upon network requirements. 3. with valid tone present at input, t pu equals time from pdwn going low until est going high. figure 10 - single-ended input con?guration ac electrical characteristics - v dd =5.0v 5%, v ss =0v, -40 c to +85 c , using test circuit shown in figure 10. characteristics sym min typ ? max units conditions 1 t i m i n g tone present detect time t dp 5 11 14 ms note 1 2 tone absent detect time t da 0.5 4 8.5 ms note 1 3 tone duration accept t rec 40 ms note 2 4 tone duration reject t rec 20 ms note 2 5 interdigit pause accept t id 40 ms note 2 6 interdigit pause reject t do 20 ms note 2 7 o u t p u t s propagation delay (st to q) t pq 811 m s toe=v dd 8 propagation delay (st to std) t pstd 12 16 m s toe=v dd 9 output data set up (q to std) t qstd 3.4 m s toe=v dd 10 propagation delay (toe to q enable) t pte 50 ns load of 10 k w , 50 pf 11 propagation delay (toe to q disable) t ptd 300 ns load of 10 k w , 50 pf 12 p d w n power-up time t pu 30 ms note 3 13 power-down time t pd 20 ms 14 c l o c k crystal/clock frequency f c 3.5759 3.5795 3.5831 mhz 15 clock input rise time t lhcl 110 ns ext. clock 16 clock input fall time t hlcl 110 ns ext. clock 17 clock input duty cycle dc cl 40 50 60 % ext. clock 18 capacitive load (osc2) c lo 30 pf in+ in- gs v ref inh pdwn osc 1 osc 2 v ss toe v dd st/gt est std q4 q3 q2 q1 dtmf input c 1 r 1 r 2 x-tal v dd c 2 r 3 notes: r 1 ,r 2 =100k w 1% r 3 =300k w 1% c 1 ,c 2 =100 nf 5% x-tal=3.579545 mhz 0.1% mt8870d/MT8870D-1
iso 2 -cmos mt8870d/MT8870D-1 4-21 figure 11 - timing diagram explanation of events explanation of symbols a) tone bursts detected, tone duration invalid, outputs not updated. b) tone #n detected, tone duration valid, tone decoded and latched in outputs c) end of tone #n detected, tone absent duration valid, outputs remian latched until next valid tone. d) outputs switched to high impedance state. e) tone #n + 1 detected, tone duration valid, tone decoded and latched in outputs (currently high impedance). f) acceptable dropout of tone #n + 1, tone absent duration invalid, outputs remain latched. g) end of tone #n + 1 detected, tone absent duration valid, outputs remain latched until next valid tone. v in dtmf composite input signal. est early steering output. indicates detection of valid tone frequencies. st/gt steering input/guard time output. drives external rc timing circuit. q 1 -q 4 4-bit decoded tone output. std delayed steering output. indicates that valid frequencies have been present/absent for the required guard time thus constituting a valid signal. toe tone output enable (input). a low level shifts q 1 -q 4 to its high impedance state. t rec maximum dtmf signal duration not deteced as valid t rec minimum dtmf signal duration required for valid recognition t id maximum time between valid dtmf signals. t do maximum allowable drop out during valid dtmf signal. t dp time to detect the presence of valid dtmf signals. t da time to detect the absence of valid dtmf signals. t gtp guard time, tone present. t gta guard time, tone absent. v in est st/gt q 1 -q 4 std toe events abc d efg t rec t rec t id t do tone #n tone #n + 1 tone #n + 1 t dp t da t gtp t gta t pq t qstd t psrd t ptd t pte # n # (n + 1) high impedance decoded tone # (n-1) v tst
mt8870d/MT8870D-1 iso 2 -cmos 4-22 notes:
package outlines plastic dual-in-line packages (pdip) - e suf?x note: controlling dimensions in parenthesis ( ) are in millimeters. dim 8-pin 16-pin 18-pin 20-pin plastic plastic plastic plastic min max min max min max min max a 0.210 (5.33) 0.210 (5.33) 0.210 (5.33) 0.210 (5.33) a 2 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) b 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) b 2 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) c 0.008 (0.203) 0.014 (0.356) 0.008 (0.203) 0.014(0.356) 0.008 (0.203) 0.014 (0.356) 0.008 (0.203) 0.014 (0.356) d 0.355 (9.02) 0.400 (10.16) 0.780 (19.81) 0.800 (20.32) 0.880 (22.35) 0.920 (23.37) 0.980 (24.89) 1.060 (26.9) d 1 0.005 (0.13) 0.005 (0.13) 0.005 (0.13) 0.005 (0.13) e 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) e 1 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) e 0.100 bsc (2.54) 0.100 bsc (2.54) 0.100 bsc (2.54) 0.100 bsc (2.54) e a 0.300 bsc (7.62) 0.300 bsc (7.62) 0.300 bsc (7.62) 0.300 bsc (7.62) l 0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81) e b 0.430 (10.92) 0.430 (10.92) 0.430 (10.92) 0.430 (10.92) e c 0 0.060 (1.52) 0 0.060 (1.52) 0 0.060 (1.52) 0 0.060 (1.52) e 1 32 1 e n-2 n-1 n l d d 1 b 2 a 2 e b c e a notes: 1) not to scale 2) dimensions in inches 3) (dimensions in millimeters) a e b e c general-8
package outlines plastic dual-in-line packages (pdip) - e suf?x dim 22-pin 24-pin 28-pin 40-pin plastic plastic plastic plastic min max min max min max min max a 0.210 (5.33) 0.250 (6.35) 0.250 (6.35) 0.250 (6.35) a 2 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) b 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) b 2 0.045 (1.15) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) c 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) d 1.050 (26.67) 1.120 (28.44) 1.150 (29.3) 1.290 (32.7) 1.380 (35.1) 1.565 (39.7) 1.980 (50.3) 2.095 (53.2) d 1 0.005 (0.13) 0.005 (0.13) 0.005 (0.13) 0.005 (0.13) e 0.390 (9.91) 0.430 (10.92) 0.600 (15.24) 0.670 (17.02) 0.600 (15.24) 0.670 (17.02) 0.600 (15.24) 0.670 (17.02) e 0.290 (7.37) .330 (8.38) e 1 0.330 (8.39) 0.380 (9.65) 0.485 (12.32) 0.580 (14.73) 0.485 (12.32) 0.580 (14.73) 0.485 (12.32) 0.580 (14.73) e 1 0.246 (6.25) 0.254 (6.45) e 0.100 bsc (2.54) 0.100 bsc (2.54) 0.100 bsc (2.54) 0.100 bsc (2.54) e a 0.400 bsc (10.16) 0.600 bsc (15.24) 0.600 bsc (15.24) 0.600 bsc (15.24) e a 0.300 bsc (7.62) e b 0.430 (10.92) l 0.115 (2.93) 0.160 (4.06) 0.115 (2.93) 0.200 (5.08) 0.115 (2.93) 0.200 (5.08) 0.115 (2.93) 0.200 (5.08) a 15 15 15 15 e 1 32 1 e n-2 n-1 n l d d 1 b 2 a 2 e b c e a notes: 1) not to scale 2) dimensions in inches 3) (dimensions in millimeters) a e b a shaded areas for 300 mil body width 24 pdip only
package outlines small shrink outline package (ssop) - n suf?x pin 1 a 1 b e d e a l h c a 2 dim 20-pin 24-pin 28-pin 48-pin min max min max min max min max a 0.079 (2) - 0.079 (2) 0.079 (2) 0.095 (2.41) 0.110 (2.79) a 1 0.002 (0.05) 0.002 (0.05) 0.002 (0.05) 0.008 (0.2) 0.016 (0.406) b 0.0087 (0.22) 0.013 (0.33) 0.0087 (0.22) 0.013 (0.33) 0.0087 (0.22) 0.013 (0.33) 0.008 (0.2) 0.0135 (0.342) c 0.008 (0.21) 0.008 (0.21) 0.008 (0.21) 0.010 (0.25) d 0.27 (6.9) 0.295 (7.5) 0.31 (7.9) 0.33 (8.5) 0.39 (9.9) 0.42 (10.5) 0.62 (15.75) 0.63 (16.00) e 0.2 (5.0) 0.22 (5.6) 0.2 (5.0) 0.22 (5.6) 0.2 (5.0) 0.22 (5.6) 0.291 (7.39) 0.299 (7.59) e 0.025 bsc (0.635 bsc) 0.025 bsc (0.635 bsc) 0.025 bsc (0.635 bsc) 0.025 bsc (0.635 bsc) a 2 0.065 (1.65) 0.073 (1.85) 0.065 (1.65) 0.073 (1.85) 0.065 (1.65) 0.073 (1.85) 0.089 (2.26) 0.099 (2.52) h 0.29 (7.4) 0.32 (8.2) 0.29 (7.4) 0.32 (8.2) 0.29 (7.4) 0.32 (8.2) 0.395 (10.03) 0.42 (10.67) l 0.022 (0.55) 0.037 (0.95) 0.022 (0.55) 0.037 (0.95) 0.022 (0.55) 0.037 (0.95) 0.02 (0.51) 0.04 (1.02) notes: 1) not to scale 2) dimensions in inches 3) (dimensions in millimeters) 4) ref. jedec standard m0-150/m0118 for 48 pin 5) a & b maximum dimensions include allowable mold flash general-11
package outlines lead soic package - s suf?x notes: 1. controlling dimensions in parenthesis ( ) are in millimeters. 2. converted inch dimensions are not necessarily exact. dim 16-pin 18-pin 20-pin 24-pin 28-pin min max min max min max min max min max a 0.093 (2.35) 0.104 (2.65) 0.093 (2.35) 0.104 (2.65) 0.093 (2.35) 0.104 (2.65) 0.093 (2.35) 0.104 (2.65) 0.093 (2.35) 0.104 (2.65) a 1 0.004 (0.10) 0.012 (0.30) 0.004 (0.10) 0.012 (0.30) 0.004 (0.10) 0.012 (0.30) 0.004 (0.10) 0.012 (0.30) 0.004 (0.10) 0.012 (0.30) b 0.013 (0.33) 0.020 (0.51) 0.013 (0.33) 0.030 (0.51) 0.013 (0.33) 0.020 (0.51) 0.013 (0.33) 0.020 (0.51) 0.013 (0.33) 0.020 (0.51) c 0.009 (0.231) 0.013 (0.318) 0.009 (0.231) 0.013 (0.318) 0.009 (0.231) 0.013 (0.318) 0.009 (0.231) 0.013 (0.318) 0.009 (0.231) 0.013 (0.318) d 0.398 (10.1) 0.413 (10.5) 0.447 (11.35) 0.4625 (11.75) 0.496 (12.60) 0.512 (13.00) 0.5985 (15.2) 0.614 (15.6) 0.697 (17.7) 0.7125 (18.1) e 0.291 (7.40) 0.299 (7.40) 0.291 (7.40) 0.299 (7.40) 0.291 (7.40) 0.299 (7.40) 0.291 (7.40) 0.299 (7.40) 0.291 (7.40) 0.299 (7.40) e 0.050 bsc (1.27 bsc) 0.050 bsc (1.27 bsc) 0.050 bsc (1.27 bsc) 0.050 bsc (1.27 bsc) 0.050 bsc (1.27 bsc) h 0.394 (10.00) 0.419 (10.65) 0.394 (10.00) 0.419 (10.65) 0.394 (10.00) 0.419 (10.65) 0.394 (10.00) 0.419 (10.65) 0.394 (10.00) 0.419 (10.65) l 0.016 (0.40) 0.050 (1.27) 0.016 (0.40) 0.050 (1.27) 0.016 (0.40) 0.050 (1.27) 0.016 (0.40) 0.050 (1.27) 0.016 (0.40) 0.050 (1.27) pin 1 a 1 b e e a l h c notes: 1) not to scale 2) dimensions in inches 3) (dimensions in millimeters) 4) a & b maximum dimensions include allowable mold flash d l 4 mils (lead coplanarity) general-7
m mitel (design) and st-bus are registered trademarks of mitel corporation mitel semiconductor is an iso 9001 registered company copyright 1999 mitel corporation all rights reserved printed in canada technical documen t a tion - n o t for resale world headquarters - canada tel: +1 (613) 592 2122 fax: +1 (613) 592 6909 north america asia/paci?c europe, middle east, tel: +1 (770) 486 0194 tel: +65 333 6193 and africa (emea) fax: +1 (770) 631 8213 fax: +65 333 6192 tel: +44 (0) 1793 518528 fax: +44 (0) 1793 518581 http://www.mitelsemi.com information relating to products and services furnished herein by mitel corporation or its subsidiaries (collectively mitel) is believed to be reliable. however, mitel assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by mitel or licensed from third parties by mitel, whatsoever. purchasers of products are also hereby noti?ed that the use of product in certain ways or in combination with mitel, or non-mitel furnished goods or services may infringe patents or other intellectual property rights owned by mitel. this publication is issued to provide information only and (unless agreed by mitel in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, their speci?cations, services and other information appearing in this publication are subject to change by mitel without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a speci?c piece of equipment. it is the users responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to perform may result in signi?cant injury or death to the user. all products and materials are sold and services provided subject to mitels conditions of sale which are available on request.

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